1. Field of Art
This disclosure generally relates to the field of nonvolatile memory, particularly non volatile memory bitcell layouts.
2. Description of the Related Art
Nonvolatile memory (NVM) refers to memory that persistently stores information bits when not powered. A nonvolatile memory bitcell (NVM bitcell) stores a single bit of data. Some types of NVM bitcells are implemented using transistors with floating gates. The amount of charge residing on a floating gate determines whether the bitcell is storing a logical “1” or a logical “0”. The floating gate is referred to as “floating” because the gate is electrically isolated from the surroundings by an oxide or dielectric. Some NVM can store more than one state in the bitcell.
In order to expand applications and reduce costs of memory devices, it is desirable to decrease the power and size requirements for NVM bitcells. One way of reducing the power and size requirements for an NVM bitcell is to reduce the thickness of the barrier between the bitcell floating gate and the bitcell channel that adds and removes charge from the floating gate. A thinner barrier allows for a smaller overall device, and lowers the amount of power required to change the logical state of the floating gate. Traditionally, NVM bitcells have consisted of a polysilicon or Si3N4 floating gate on top of a barrier of SiO2, also called a gate oxide. In order to make a smaller device that draws less power, bitcell manufacturers have decreased the effective thickness of the gate oxide by replacing traditional SiO2 gate oxides with higher dielectric constant (high-K) materials. Manufacturers of logic devices that do not need to store a state persistently can scale the gate oxide thickness more aggressively and change the material more easily than manufactures of NVM.
The high-K materials used as gate oxides contain traps. Traps are defects in the barrier that electrons can move in and out of Electrons are capable of moving from one trap to another if the traps are in close proximity. This trap hopping is called trap assisted leakage. Trap assisted leakage prevents long term data storage in an NVM bitcell. Even if there is a barrier that prevents electrons from leaking to another node, traps close to the floating gate can cause bitcells including a high-K barrier to experience a memory effect. The memory effect is caused when traps become filled with charge carriers transmitted through the barrier when charge is added or removed from the floating gate. When the floating gate is programmed to the opposite state, charge stored in the traps migrates back to the floating gate over time. This causes the floating gate to revert back or partially revert back to its prior state. If there are enough filled traps, the memory effect can become severe enough to make it difficult to maintain two different logical states (e.g., 0 and 1) on the bitcell. The memory effect can be compensated for by over-programming. However, over-programming can cause other problems such as causing the barrier dielectric to wear out, or the inability to perform future write operations.
With traditional gate oxide type barriers, the memory effect is not a significant problem, as gate oxides such as SiO2 generally have very few traps. High-K materials, however, are trap rich, such that the memory effect is a significant problem. In addition to the memory effect problem, traps can cause other problems such as random telegraph noise (i.e., threshold voltage variation).